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Samsung Electronics develops CXL-based next-generation DRAM memory technology for first time in industry

Samsung Electronics develops CXL-based next-generation DRAM memory technology for first time in industry ANI | Updated: May 12, 2021 07:35 IST Seoul [South Korea], May 12 (ANI/Global Economic): Samsung Electronics announced Tuesday that it has developed DRAM memory technology based on the next-generation interface Compute Express Link (CXL) for the first time in the industry. Samsung Electronics has secured the next-generation semiconductor technology leadership through the development of high-capacity, high-bandwidth DRAM technology that can dramatically improve the performance of data centers in terms of artificial intelligence, machine learning, and big data. Samsung Electronics has verified the CXL-based DRAM memory developed this time on Intel s platform to secure the base technology for a large-capacity DRAM solution required by the next-generation data center, and expand cooperation with major global data centers and cloud companies

Soult ukpyolsiSouth koreaSamsung electronicsEnterprise data centerGlobal economicExpress linkData centerRam memory technologyExt generation interfaceதெற்கு கொரியாசாம்சங் மின்னணுவியல்நிறுவன தகவல்கள் மையம்உலகளாவிய பொருளாதாரஎக்ஸ்பிரஸ் இணைப்புதகவல்கள் மையம்

Samsung develops next-generation DRAM memory

Samsung develops next-generation DRAM memory ANI 12 May 2021, 12:18 GMT+10 Seoul [South Korea], May 12 (ANI/Global Economic): Samsung Electronics announced Tuesday that it has developed DRAM memory technology based on the next-generation interface Compute Express Link (CXL) for the first time in the industry. Samsung Electronics has secured the next-generation semiconductor technology leadership through the development of high-capacity, high-bandwidth DRAM technology that can dramatically improve the performance of data centers in terms of artificial intelligence, machine learning, and big data. Samsung Electronics has verified the CXL-based DRAM memory developed this time on Intel s platform to secure the base technology for a large-capacity DRAM solution required by the next-generation data center, and expand cooperation with major global data centers and cloud companies.

Soult ukpyolsiSouth koreaSamsung electronicsEnterprise data centerGlobal economicExpress linkBreaking technology newsData centersCenters andFirst timeதெற்கு கொரியாசாம்சங் மின்னணுவியல்நிறுவன தகவல்கள் மையம்உலகளாவிய பொருளாதாரஎக்ஸ்பிரஸ் இணைப்புஉடைத்தல் தொழில்நுட்பம் செய்தி

Samsung unveils CXL-based DDR5, an industry-first innovation

May 11, 2021 01:26 EDT with 0 comments Samsung has arguablyturned its memory technology innovation all the way up to 11 recently. Earlier this year, the company announced the revolutionary AI-based HBM-PIM memory and today, it has announced the industry s first DDR5 memory solution to run on the Compute Express Link (CXL) interface. The South Korean giant says that the next-gen DDR standard will enable the movement of enormous amounts of data due to the massive capacities that it will offer. Of course, these high-capacity memory modules aren t built for home usage, at least not for the foreseeable future, and are instead designed for high-performance computing needs like AI, big data, and more. As such, moving to the CXL standard will be helpful for IT industries.

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Micron Abandoning 3D Xpoint in Favour for CXL

Micron Abandoning 3D Xpoint in Favour for CXL Recently, Micron announced that it is dropping the development of 3D Xpoint memory in favour of CXL. What is 3D Xpoint, what is CXL, and why is Micron changing tact? What is 3D Xpoint memory? 3D Xpoint memory is a non-volatile memory technology that was developed by Intel and Micron. The technology, unlike NAND FLASH, allows for individual bits to be accessed which can provide it enhanced performance over NAND (which has to have entire blocks erased before bits can be altered). The memory technology utilises bulk resistance to store data, and while the exact material used between bit lines has not been publicly stated, what is known is that the technology utilises Chalcogenide glass. The bits are arranged so that each bit has two metal connectors (top and bottom), and a current is passed through one of the connectors. The resistance of the channel is measured, and this indicates the state of the bit.

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PLDA Announces a Unique CXL Verification IP Ecosystem, Delivering Robust Verification That Reduces Time-to-Design for CXL 2 0 Applications

PLDA Announces a Unique CXL Verification IP Ecosystem, Delivering Robust Verification That Reduces Time-to-Design for CXL 2 0 Applications
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