Controller IP for PCIe 5.0 Targeting Automotive The configurable and scalable DesignWare Controller IP for PCI Express (PCIe) supports all required features of the PCI Express 5.0, 4.0, 3.1, 2.1, 1.1 and PHY Interface for PCI Express (PIPE) specifications, and can be configured by the user to support Endpoint (EP), Root Port, Dual Mode (DM), or Switch Port (SW) applications. The high-quality, synthesizable IP portfolio is available in your choice of datapath widths, PIPE interface widths, operating frequencies, and over 1200 configuration parameters, all working together to enable designers to optimize their applications for size, power, latency and throughput. The DesignWare Controller IP portfolio for PCI Express integrates quickly and easily into system-on-chip (SoC) designs with a user-friendly application interface or an industry standard AMBA interface, and conservative timing suitable for a wide range of ASIC and FPGA technologies.
Synopsys To Expand DesignWare Ethernet IP Portfolio with Acquisition of MorethanIP
Acquisition Will Enable Synopsys to Deliver a Complete Ethernet IP Solution, Consisting of MAC, PCS and 112G PHY for 200G/400G and 800G High-Performance Computing SoCs
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MOUNTAIN VIEW, Calif., April 12, 2021 /PRNewswire/ Synopsys, Inc. (Nasdaq: SNPS) today announced it has signed a definitive agreement to acquire MorethanIP, a provider of Ethernet Digital Controller IP supporting data rates from 10G to 800G. This acquisition will expand Synopsys DesignWare® Ethernet Controller IP portfolio with the addition of MAC and PCS for 200G/400G and 800G Ethernet, providing customers with a complete low-latency, high-performance Ethernet IP solution for networking, AI, and cloud computing SoCs. The acquired MAC and PCS IP will complement Synopsys existing 112G Ethernet PHY IP solution. The acquisition also adds a team of experienced R&D engineers wit
PHY IP for PCIe 5.0 in TSMC N7 The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®) 5.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for higher bandwidth. The PHY meets the needs of today’s high-speed chipto-chip, board-to-board, and backplane interfaces while being extremely low in power and area.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipmen
® EV Development Toolkit. By using Synopsys programmable ARC EV Processor, Kyocera successfully integrated high-performance artificial intelligence (AI) processing capabilities such as super resolution, with the flexibility to support future AI models. In addition, Kyocera deployed Synopsys HAPS
® FPGA-based prototyping system to accelerate ARC EV software development, SoC integration, and system validation. Implementing advanced AI functionality into our MFP SoC required high-performance, low-power processor IP with a high-quality tool chain, allowing us to find and test AI algorithms while developing the SoC in parallel, said Michihiro Okada, general manager, software development division at Kyocera Document Solutions Inc. Only Synopsys DesignWare ARC EV Processor IP and mature MetaWare EV Toolkit met our extensibility, performance, and area requirements.
Highlights
® 5.0 or CXL™ 2.0 architectures
Pre-verified with DesignWare Controller IP for PCI Express technology and CXL enables fast integration and lowers risk
Efficient encryption/decryption and authentication with AES-GCM helps ensure data confidentiality and integrity for high-performance systems
Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of the DesignWare
® Integrity and Data Encryption (IDE) Security Modules to help designers protect against data tampering and physical attacks in high-performance computing (HPC) SoCs using the PCI Express
® (PCIe
™ (CXL
™) 2.0 interface. The DesignWare IDE Security Modules protect sensitive data with efficient encryption, decryption, and authentication based on AES-GCM algorithms while meeting PCIe 5.0 specification and CXL 2.0 IP performance and latency requirements. The DesignWare IDE Security Modules are designed to the latest PCIe 5.0 specification and CXL 2.0 interface standards and are designed an